A clock distribution network is required for controlling the flow of data along critical logic paths in high-speed integrated circuit devices such as microprocessors and application specific integrated circuits, for example. However, current clock distribution networks suffer from unknown (or unpredictable) components of global and local skew and jitter. Extrapolated trends of skew and jitter for high performance microprocessors, for example, indicate a need for clock distribution networks that can reduce or eliminate unknown components of timing uncertainty for systems operating with local clock frequencies greater than 20 GHz. A reference related to such trends can be found in A. V. Mule, E. N. Glytsis, T. K. Gaylord, and J. D. Meindl, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 5, pp. 582–594, October 2002.
Intra-chip optical clock distribution networks previously investigated in the literature propose the use of global guided-wave distribution systems that communicate over a fixed-fanout distribution with optoelectronic receivers. Such distribution systems may address only a limited portion of the timing uncertainty associated with global and semi-global levels of electrical wiring and clock drivers, as the varying path length and internal scattering may contribute additional skew and jitter that matches or even exceeds that of the purely electrical system. In addition, optoelectronic receivers contribute additional electrical power dissipation, which unless managed properly, may negate any power reduction achieved by using optics.
Thus, a heretofore unaddressed need exists in industries employing clock distribution systems that addresses the aforementioned deficiencies and/or inadequacies.